Co-integration of bulk and SOI transistors
US10714501B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Aug 7, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.