Apparatuses and methods for using look-ahead duty cycle correction to determine duty cycle adjustment values while a semiconductor device remains in operation
US10715127B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.