Cache and compression interoperability in a graphics processor pipeline
US10719447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2016 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.