Systems and methods involving multi-bank, dual-pipe memory circuitry
US10720205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2015 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Jun 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe SRAMs and methods herein may also comprise features for capturing two beats of write data, splitting and/or combining them via one or more splitting/combining processes, and bussing them to each SRAM bank, where they may be split/combined/recombined via one or more processes to write data to particular memory bank(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.