Method of forming vertical transistor device
US10720363B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 11, 2018 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.