Memory array with ferroelectric elements
US10720438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.