Daniel H. Morris
37Patents
4h-index
23Co-inventors
55Inventor score
Filing activity: Dec 18, 2014 → Oct 1, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10651182B2 | Three-dimensional ferroelectric NOR-type memory | Electricity | 14 | Active |
| US11355505B2 | Vertical backend transistor with ferroelectric material | Electricity | 7 | Active |
| US10749104B2 | Combinatorial magneto electric spin orbit logic | Electricity | 5 | Active |
| US11037614B2 | Imprint-free write driver for ferroelectric memory | Electricity | 4 | Active |
| US10998339B2 | One transistor and ferroelectric FET based memory cell | Electricity | 3 | Active |
| US10748602B2 | Nonvolatile SRAM | Physics | 2 | Active |
| US9985611B2 | Tunnel field-effect transistor (TFET) based high-density and low-power sequential | Electricity | 2 | Active |
| US10832761B2 | Polarization gate stack SRAM | Physics | 2 | Active |
| US10573385B2 | Ferroelectric based memory cell with non-volatile retention | Electricity | 1 | Active |
| US11171145B2 | Memory devices based on capacitors with built-in electric field | Electricity | 1 | Active |
| US11450675B2 | One transistor and one ferroelectric capacitor memory cells in diagonal arrangements | Electricity | 1 | Active |
| US10559349B2 | Polarization gate stack SRAM | Physics | 1 | Active |
| US10261923B2 | Configurable interconnect apparatus and method | Emerging Cross-Sectional Technologies | 1 | Active |
| US11735652B2 | Field effect transistors having ferroelectric or antiferroelectric gate dielectric structure | Electricity | 0 | Active |
| US10901486B2 | Configurable interconnect apparatus and method | Emerging Cross-Sectional Technologies | 0 | Active |
| US9490780B2 | Apparatuses, methods, and systems for dense circuitry using tunnel field effect transistors | Physics | 0 | Active |
| US11355504B2 | Anti-ferroelectric capacitor memory cell | Electricity | 0 | Active |
| US11322504B2 | Ferroelectric-capacitor integration using novel multi-metal-level interconnect with replaced dielectric for ultra-dense embedded SRAM in state-of-the-art CMOS technology | Electricity | 0 | Active |
| US9997227B2 | Non-volatile ferroelectric logic with granular power-gating | Electricity | 0 | Active |
| US10720438B2 | Memory array with ferroelectric elements | Electricity | 0 | Active |
| US10553694B2 | Transistors with temperature compensating gate structures | Electricity | 0 | Active |
| US10886286B2 | Vertical memory control circuitry located in interconnect layers | Electricity | 0 | Active |
| US11502103B2 | Memory cell with a ferroelectric capacitor integrated with a transtor gate | Electricity | 0 | Active |
| US10355005B2 | Semi-volatile embedded memory with between-fin floating-gate device and method | Electricity | 0 | Active |
| US10777250B2 | Save-restore circuitry with metal-ferroelectric-metal devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.