Field-effect transistors with airgaps
US10720494B2 · kind B2 · utility
1Cited by
21References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2018 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Jan 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/679
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.