Structure and method for forming fully-aligned trench with an up-via integration scheme
US10727124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.