Three-dimensional monolithic vertical field effect transistor logic gates
US10727139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jan 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83896
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.