Method for controlling core critical dimension variation using flash trim sequence
US10727143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jul 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.