Circuits constructed from stacked field-effect transistors

US10727236B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Nan Wu · Beijing, CN
• Peter Baars · Dresden, DE

Key dates

• Filing date: Dec 21, 2018
• Grant date: Jul 28, 2020
• Expiry date: Dec 21, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors. A structure includes a first fin, a second fin arranged over the first fin, a first dielectric layer between the first fin and the second fin, and a first inverter. The first inverter includes a first field-effect transistor with a channel region in the first fin and a second field-effect transistor with a channel region in the second fin. The first field-effect transistor and the second field-effect transistor share a first gate structure having an overlapping arrangement with the channel region in the first fin and the channel region in the second fin. The first fin has a longitudinal axis, and the second fin has a longitudinal axis that is aligned at an angle relative to the longitudinal axis of the first fin.