Inventor · Dresden, DE

Peter Baars

107Patents

9h-index

86Co-inventors

79Inventor score

Filing activity: Aug 15, 2005 → Jun 2, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8557666B2	Methods for fabricating integrated circuits	Electricity	25	Active
US8647938B1	SRAM integrated circuits with buried saddle-shaped FINFET and methods for their fabrication	Electricity	20	Active
US8735232B2	Methods for forming semiconductor devices	Electricity	17	Active
US9349842B2	Methods of forming semiconductor devices comprising ferroelectric elements and fast high-K metal gate transistors	Electricity	12	Active
US8722523B2	Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure	Electricity	11	Active
US9608110B2	Methods of forming a semiconductor circuit element and semiconductor circuit element	Electricity	11	Active
US9806170B1	Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI	Electricity	10	Active
US10157774B1	Contact scheme for landing on different contact area levels	Electricity	10	Active
US9673210B1	Semiconductor structure including a nonvolatile memory cell having a charge trapping layer and method for the formation thereof	Electricity	9	Active
US9634017B1	Semiconductor structure including a nonvolatile memory cell and method for the formation thereof	Electricity	8	Active
US7659602B2	Semiconductor component with MIM capacitor	Electricity	8	Active
US8927407B2	Method of forming self-aligned contacts for a semiconductor device	Electricity	8	Active
US8652889B2	Fin-transistor formed on a patterned STI region by late fin etch	Electricity	7	Active
US7851356B2	Integrated circuit and methods of manufacturing the same	Electricity	7	Active
US7371645B2	Method of manufacturing a field effect transistor device with recessed channel and corner gate device	Electricity	6	Expired
US8357978B1	Methods of forming semiconductor devices with replacement gate structures	Electricity	6	Active
US8614123B2	Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures	Electricity	6	Active
US9929148B1	Semiconductor device including buried capacitive structures and a method of forming the same	Electricity	6	Active
US8399352B2	Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions	Electricity	6	Active
US8742510B2	Semiconductor devices with replacement gate structures having conductive contacts positioned therebetween	Electricity	6	Active
US8846513B2	Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill	Electricity	5	Active
US8609457B2	Semiconductor device with DRAM bit lines made from same material as gate electrodes in non-memory regions of the device, and methods of making same	Electricity	4	Active
US8916433B2	Superior integrity of high-k metal gate stacks by capping STI regions	Electricity	4	Active
US9136175B2	Methods for fabricating integrated circuits	Electricity	4	Active
US9337045B2	Methods of forming a semiconductor circuit element and semiconductor circuit element	Electricity	4	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.