Dual metal gate structures for advanced integrated circuit structure fabrication

US10727313B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jeffrey S. Leib · Beaverton, US
• Jenny Hu · Santa Clara, US
• Anindya Dasgupta · Hillsboro, US
• Michael L. Hattendorf · Beaverton, US
• Christopher P. Auth · Portland, US

Key dates

• Filing date: Dec 30, 2017
• Grant date: Jul 28, 2020
• Expiry date: Jan 17, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0149
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.