Vertically-integrated two-dimensional (2D) semiconductor slabs in complementary field effect transistor (CFET) cell circuits, and method of fabricating
US10734384B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2019 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Jan 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Vertically-integrated two-dimensional (2D) semiconductor slabs in Complementary Field-Effect Transistor (FET) (CFET) cell circuits are disclosed. A horizontal footprint of a CFET cell circuit may be reduced in an X-axis dimension by reducing a gate length of the N-type and P-type channel structures. The N-type and P-type channel structures may be formed of 2D semiconductor materials with high carrier mobility and strong on/off control, which allows a gate length of each semiconductor channel structure to be reduced without increasing a leakage current. By employing one or more elongated monolayers of 2D material in each slab, and vertically stacking slabs to form each semiconductor channel structure, a desired CFET drive strength may be adjusted according to a vertical dimension of the CFET cell circuit, while X-axis and Y-axis dimensions of the horizontal footprint are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.