Conductive contacts in semiconductor on insulator substrate
US10734410B2 · kind B2 · utility
3Cited by
10References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2017 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Jul 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.