Conditional construct splitting for latency hiding
US10740074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.