Operation of a multi-slice processor implementing load-hit-store handling
US10740107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Feb 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices and an instruction sequencing unit. Operation of such a multi-slice processor includes: receiving, at the instruction sequencing unit, a load instruction indicating load address data and a load data length; determining a previous store instruction in an issue queue such that store address data for the previous store instruction corresponds to the load address data, wherein the previous store instruction corresponds to a store data length; and generating, in dependence upon the store data length matching the load data length, an indication in the issue queue that indicates a dependency between the load instruction and the previous store instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.