Integrated circuit design system with automatic timing margin reduction
US10740526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for manufacturing an integrated circuit chip is disclosed. The method includes selecting cell-based circuit representations to define an initial circuit design. The initial circuit design is partitioned into multiple sub-design blocks to define a partitioned design. Circuit representations of local clock sources are inserted into the partitioned design. Each local clock source is for clocking a respective sub-design block and based on a global clock source. A timing analysis is performed to estimate skew between each local clock source and the global clock source. The partitioned design is automatically modified based on the estimated skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.