Method and device for embedding flash memory and logic integration in FinFET technology
US10741552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.