Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication

US10741669B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Jeffrey S. Leib · Beaverton, US
• Jenny Hu · Santa Clara, US
• Anindya Dasgupta · Hillsboro, US
• Michael L. Hattendorf · Beaverton, US
• Christopher P. Auth · Portland, US

Key dates

• Filing date: Dec 30, 2017
• Grant date: Aug 11, 2020
• Expiry date: Dec 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0149
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.