Patent · US Active

Constrained pseudorandom test pattern for in-system logic built-in self-test

US10746790B1 · kind B1 · utility

5Cited by
7References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 25, 2019
Grant dateAug 18, 2020
Priority date
Expiry dateMar 25, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/3187
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Embodiments of the invention are directed to a built-in self-test system for an electronic circuit. The system includes a memory having two or more base seeds stored thereon. The system further includes seed generation logic configured to generate, based at least in part on the two or more base seeds, a plurality of generated seeds. The generated seeds can be constructed from the base seeds such that each of the generated seeds encodes a test pattern that satisfies a functional constraint. A finite state machine is configured to generate, based on the plurality of generated seeds, a sequence of constrained pseudorandom test patterns. A test controller is operable to place the electronic circuit into a test mode based on the constrained pseudorandom test pattern.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.