Patent · US Active

Test circuitry with annularly arranged compressor and decompressor elements

US10747922B1 · kind B1 · utility

0Cited by

5References

13Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Akhil Garg · Sidhauli, IN
Sahil Jain · Ghaziabad, IN
Vivek Chickermane · Ithaca, US

Key dates

Filing date	Apr 18, 2018
Grant date	Aug 18, 2020
Priority date	—
Expiry date	Aug 3, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/333
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.