Dynamic programing of valley margins of a memory cell
US10748625B1 · kind B1 · utility
7Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2019 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5625
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.