Methods and systems for patterning of low aspect ratio stacks

US10748769B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Elliott Franke · Albany, US
• Angelique Raley · Halfmoon, US
• Sophie Thibaut · Albany, US

Key dates

• Filing date: May 8, 2019
• Grant date: Aug 18, 2020
• Expiry date: May 8, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/67069
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).