Patent · US Active

Embedded etch rate reference layer for enhanced etch time precision

US10748823B2 · kind B2 · utility

0Cited by

13References

13Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Yann Mignot · Slingerlands, US
Alan C. Thomas · Gilbert, US
Daniel P. Sanders · San Jose, US
Dario L. Goldfarb · Potsdam, US
Nelson Felix · Slingerlands, US
Chi-Chun Liu · Altamont, US
John C. Arnold · North Chatham, US

Key dates

Filing date	Sep 27, 2018
Grant date	Aug 18, 2020
Priority date	—
Expiry date	Sep 27, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/12
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.