Area selective cyclic deposition for VFET top spacer
US10749011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Oct 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.