Spacer with laminate liner
US10755918B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2018 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to a spacer with laminate liner and methods of manufacture. The structure includes: a replacement metal gate structure; a laminate low-k liner on the replacement metal gate structure; and a spacer on the laminate low-k liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.