Multi-package top-side-cooling

US10755999B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Ralf Otremba · Kaufbeuren, DE
• Uwe Kirchner · Feldkirchen in Kärnten, AT
• Matteo-Alessandro Kutschak · Ludmannsdorf, DE
• Klaus Schiess · Allensbach, DE
• Bernd Schmoelzer · Radenthein, AT

Key dates

• Filing date: Mar 25, 2019
• Grant date: Aug 25, 2020
• Expiry date: Mar 25, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2023/4087
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A power semiconductor arrangement includes a carrier and packages. Each package: encloses a power semiconductor die having first and second load terminals and configured to conduct a die load current between the load terminals; has a package body with a top side, a footprint side and sidewalls extending from the footprint side to the top side; a lead frame structure configured to electrically and mechanically couple the package to the carrier with the package footprint side facing the carrier, the lead frame structure including at least one first outside terminal electrically connected with the first load terminal of the die; a top layer arranged at the package top side and electrically connected with the second load terminal of the die. A top heatsink is attached to each package top layer, electrically contacted to each package top layer, and configured to conduct at least a sum of the die load currents.