Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers
US10756078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2017 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Mar 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.