Inventor · Forest Grove, OR, US

Nathan Jack

17Patents
2h-index
28Co-inventors
50Inventor score

Filing activity: Jun 15, 2007 → Jan 9, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US7831205B2 Methods and systems for wireless communication by magnetic induction Electricity 36 Active
US11824116B2 Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact Electricity 2 Active
US11908856B2 Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact Performing Operations; Transporting 2 Active
US9435841B2 Integrated circuit protection during high-current ESD testing Electricity 1 Active
US9219055B2 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers Electricity 1 Active
US9869708B2 Integrated circuit protection during high-current ESD testing Electricity 1 Active
US12402349B2 Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact Electricity 0 Active
US9620497B2 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers Electricity 0 Active
US12288789B2 Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact Performing Operations; Transporting 0 Active
US12328947B2 Substrate-less silicon controlled rectifier (SCR) integrated circuit structures Electricity 0 Active
US12317590B2 Substrate-free integrated circuit structures Electricity 0 Active
US11837641B2 Gate-all-around integrated circuit structures having adjacent deep via substrate contacts for sub-fin electrical contact Electricity 0 Active
US10756078B2 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers Electricity 0 Active
US10359461B2 Integrated circuit protection during high-current ESD testing Electricity 0 Active
US11652107B2 Substrate-less FinFET diode architectures with backside metal contact and subfin regions Electricity 0 Active
US10181463B2 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers Electricity 0 Active
US11264405B2 Semiconductor diodes employing back-side semiconductor or metal Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.