Multiple-stacked semiconductor nanowires and source/drain spacers
US10756174B2 · kind B2 · utility
7Cited by
2References
18Claims
0Family size
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Key dates
| Filing date | Jun 5, 2017 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Jul 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.