Integrated circuit skew determination
US10756711B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2019 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Nov 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.