Interconnect fabric link width reduction to reduce instantaneous power consumption
US10761589B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.