Single plate configuration and memory array operation
US10762944B2 · kind B2 · utility
2Cited by
17References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2257
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.