Inspection method for memory integrity, nonvolatile memory and electronic device
US10762970B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An inspection method for memory integrity, a non-volatile memory, and an electronic device are provided. The method includes following steps. A threshold voltage of at least one memory cell to-be-inspected in a non-volatile memory is obtained. A data value belonging to the at least one memory cell to-be-inspected is determined by comparing a read voltage and the threshold voltage. When the data value belonging to the at least one memory cell to-be-inspected is determined, a preset voltage is set according to the data value. An offset data value belonging to the at least one memory cell to-be-inspected is obtained by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected. And, whether the data value and the offset data value belonging to the at least one memory cell to-be-inspected are the same is determined, so as to determine whether an integrity of the memory cell to-be-inspected is defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.