Semiconductor device including buried insulation layer and manufacturing method thereof
US10763170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Aug 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.