Multi-row wiring member for semiconductor device and method for manufacturing the same
US10763202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Nov 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-row wiring member configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in a bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at a margin around an aggregate of individual wiring members arrayed in the matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.