Method for manufacturing electronic package
US10763237B2 · kind B2 · utility
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0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.