Multi-layer silicon/gallium nitride semiconductor

US10763248B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sansaptak Dasgupta · Hillsboro, US
• Marko Radosavljevic · Portland, US
• Han Wui Then · Portland, US
• Ravi Pillarisetty · Portland, US
• Kimin Jun · Hillsboro, US
• Patrick Morrow · Portland, US
• Valluri Rao · Saratoga, US
• Paul B. Fischer · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Sep 24, 2015
• Grant date: Sep 1, 2020
• Expiry date: Sep 3, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.