Method for forming a flat bottom electrode via (BEVA) top surface for memory
US10763426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Aug 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.