Main-auxiliary field-effect transistor configurations with interior parallel transistors
US10763847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Dec 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of main FETs coupled in series and an auxiliary FET coupled in parallel with an interior FET of the plurality of main FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.