Method for processing a layer structure and microelectromechanical component
US10766766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C1/00595
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.