Semiconductor storage device
US10770117B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device includes a source line, a first selection line, word lines, a dummy word line, and a second selection line. A first pillar having a first semiconductor layer extends through the first selection line, the word lines, and the first dummy word line and is connected to the source line. Memory cells are at intersections of the word lines and the first pillar. A conductive layer is on the first semiconductor layer and extends into the first dummy word line. A second pillar with a second semiconductor layer extends through the second selection line and contacts the conductive layer. A bit line is electrically connected to the second semiconductor layer. A control circuit is configured to apply voltages to the various lines during an erasing of the memory cells. A voltage between a source line voltage and a world line voltage is applied to dummy word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.