Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10770133B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.