Bob Haig
14Patents
8h-index
7Co-inventors
54Inventor score
Filing activity: Aug 23, 2018 → Oct 28, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10777262B1 | Read data processing circuits and methods associated memory cells | Physics | 22 | Active |
| US10770133B1 | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits | Physics | 19 | Active |
| US10877731B1 | Processing array device that performs one cycle full adder operation and bit line read/write logic features | Electricity | 17 | Active |
| US10847213B1 | Write data processing circuits and methods associated with computational memory cells | Electricity | 13 | Active |
| US10891076B1 | Results processing circuits and methods associated with computational memory cells | Physics | 13 | Active |
| US10847212B1 | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers | Physics | 13 | Active |
| US10860320B1 | Orthogonal data transposition system and method during data transfers to/from a processing array | Physics | 12 | Active |
| US10930341B1 | Processing array device that performs one cycle full adder operation and bit line read/write logic features | Electricity | 10 | Active |
| US11094374B1 | Write data processing circuits and methods associated with computational memory cells | Electricity | 6 | Active |
| US11205476B1 | Read data processing circuits and methods associated with computational memory cells | Physics | 3 | Active |
| US11409528B2 | Orthogonal data transposition system and method during data transfers to/from a processing array | Physics | 1 | Active |
| US11194519B2 | Results processing circuits and methods associated with computational memory cells | Physics | 0 | Active |
| US11257540B2 | Write data processing methods associated with computational memory cells | Electricity | 0 | Active |
| US11194548B2 | Processing array device that performs one cycle full adder operation and bit line read/write logic features | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.