Patent · US Active

Reducing chip latency at a clock boundary by reference clock phase adjustment

US10771068B2 · kind B2 · utility

0Cited by

4References

14Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Steven R. Carlough · Poughkeepsie, US
Susan M. Eickhoff · Hopewell Junction, US
Michael W. Harper · Round Rock, US
Michael B. Spear · Round Rock, US
Gary A. Van Huben · Poughkeepsie, US

Key dates

Filing date	Feb 20, 2018
Grant date	Sep 8, 2020
Priority date	—
Expiry date	Nov 12, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2205/061
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.