Faster sparse flush recovery by creating groups that are marked based on an instruction type
US10776123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for performing efficient processor pipeline flush recovery are disclosed. A processor core includes a retire queue for storing information of outstanding instructions. When the retire queue logic detects that a pipeline flush condition occurs, the logic creates one or more groups of entries in the retire queue. The logic begins the groups with an entry storing information for a youngest outstanding instruction, and creates other groups in a contiguous manner after creating this first group. The logic marks with a first indication a given group when the given group includes one or more instructions of a given type. The logic marks with a second indication the given group when the given group does not include an instruction of the given type. The logic sends to flush recovery logic information of one or more entries in only groups marked with the first indication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.