Patent · US Active

False path timing exception handler circuit

US10776546B2 · kind B2 · utility

1Cited by

8References

2Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Wilson Pradeep · Savanuru, IN
Prakash Narayanan · Bengaluru, IN
Saket Jalan · Bengaluru, IN

Key dates

Filing date	May 13, 2019
Grant date	Sep 15, 2020
Priority date	—
Expiry date	May 13, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/17
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.