Read data processing circuits and methods associated memory cells
US10777262B1 · kind B1 · utility
22Cited by
259References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.